A typical data processing system includes a processor coupled to one or more devices. The devices may include, for example, peripheral devices. Peripheral devices typically have specific functions, and are often input/output (I/O) devices. For example, a typical personal computer (PC) system includes a processor coupled to a monitor, a mouse, a keyboard, and a printer. The monitor and the printer are output devices, while the mouse and the keyboard are input devices. A compact disk (CD) read-write drive is an example of a peripheral device that is both an input device and an output device.
A coprocessor is a special purpose processing unit that assists a processor in performing certain types of operations, particularly computationally demanding operations. For example, a data processing system may include a processor coupled to a math (numeric) coprocessor, wherein the math coprocessor performs certain mathematical computations, particularly floating-point operations. In addition to math coprocessors, graphics coprocessors for manipulating graphic images are also common.
In known data processing systems including processors coupled to coprocessors, the processor executes instructions from one instruction set (e.g., processor instructions of a processor instruction set), and the coprocessor executes instructions from another instruction set (e.g., coprocessor instructions of a coprocessor instruction set). Due to the special purpose nature of coprocessors, the processor and coprocessor instruction sets typically differ substantially, and are defined by manufacturers of the processor and coprocessor, respectively.
To take advantage of the coprocessor, software programs must be written to include coprocessor instructions of the coprocessor instruction set. When the processor is executing instructions of a software program and encounters a coprocessor instruction, the processor issues the coprocessor instruction to the coprocessor. The coprocessor executes the coprocessor instruction, and typically returns a result to the processor.
A bus is a set of wires, lines or connections used to transfer signals. Buses are commonly used to transfer data between components of electronic systems such as data processing systems. For example, the typical PC system includes a higher speed local bus to accommodate higher speed components (e.g., the monitor) and a lower speed expansion bus for lower speed devices (e.g., the mouse, the keyboard, and the printer).
Many modem processors employ a technique called pipelining to execute more software program instructions (instructions) per unit of time. In general, processor execution of an instruction involves fetching the instruction (e.g., from a memory system), decoding the instruction, obtaining needed operands, using the operands to perform an operation specified by the instruction, and saving a result. In a pipelined processor, the various steps of instruction execution are performed by independent units called pipeline stages. In the pipeline stages, corresponding steps of instruction execution are performed on different instructions independently, and intermediate results are passed to successive stages. By permitting the processor to overlap the executions of multiple instructions, pipelining allows the processor to execute more instructions per unit of time.
In general, a “scalar” processor issues instructions for execution one at a time, and a “superscalar” processor is capable of issuing multiple instructions for execution at the same time. A pipelined scalar processor concurrently executes multiple instructions in different pipeline stages; the executions of the multiple instructions are overlapped as described above. A pipelined superscalar processor, on the other hand, concurrently executes multiple instructions in different pipeline stages, and is also capable of concurrently executing multiple instructions in the same pipeline stage.
As used herein, the term “interrupt request signal,” or simply “interrupt signal,” refers to a control signal which indicates a high-priority request for service. For example, a peripheral device connected to a processor may assert an interrupt signal when ready to transmit data to the processor, or to receive data from the processor. It is noted that an interrupt signal generated external to a processor may not be synchronized with a clock signal of the processor.
The two general categories of types of interrupt signals are “non-maskable” and “maskable.” The typical processor described above also has a non-maskable interrupt (NMI) terminal for receiving an NMI signal, and a maskable interrupt (IRQ) terminal for receiving an IRQ signal. The NMI signal is typically asserted when a catastrophic event has occurred or is about to occur. Examples of non-maskable interrupts include bus parity error, failure of a critical hardware component such as a timer, and imminent loss of electrical power.
In general, maskable interrupts are lower-priority requests for service that need not be tended to immediately. Maskable interrupts may be ignored by the processor under program control. A request for service from a peripheral device which is ready to transmit data to a processor, or receive data from the processor, is an example of a maskable interrupt. An interrupt controller (e.g., a programmable interrupt controller or PIC) connected to the processor typically receives maskable interrupt requests from devices connected to the processor, and prioritizes the interrupt requests.
When a processor receives an interrupt, application program execution stops, the contents of certain critical registers are saved (e.g., the internal state of the processor is saved), and internal control is transferred to an interrupt service routine (e.g., an interrupt handler) which corresponds to the type of interrupt received. In the case of a maskable or non-maskable interrupt, the interrupt controller typically identifies the interrupt to be serviced.
In a vectored interrupt system, the interrupt controller typically provides a number or instruction address assigned to the interrupt to an instruction sequencing module of the processor (e.g., during an interrupt acknowledge operation). A non-maskable interrupt is typically assigned a specific interrupt number. The processor uses the interrupt number as an index into the interrupt vector table to obtain the address of the appropriate interrupt service routine. When the interrupt service routine is completed, the saved contents of the critical registers are restored (e.g., the state of the processor is restored), and the processor resumes application program execution at the point where execution was interrupted.